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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 15 single ended LVCMOS/LVTTL outputs, 7 typical output impedance * Selectable LVCMOS/LVTTL or LVPECL clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum input frequency: 250MHz * Output skew: 250ps (maximum) * Part-to-part skew: 1.0ns (maximum) * Bank skew: 65ps (maximum) * 3.3V or 2.5V supply voltage * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
ICS87949I-147
GENERAL DESCRIPTION
The ICS87949I-147 is a low skew, /1, /2 LVCMOS/LVTTL Clock Generator and a member HiPerClockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87949I-147 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87949I-147 is characterized at 3.3V and 2.5V. Guaranteed output and part-to-part skew characteristics make the ICS87949I-147 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL 1 DIV_SELA 0 QB0:QB2 1 DIV_SELB 0 QC0:QC3 1 DIV_SELC 0 QD0:QD5 1 DIV_SELD MR/nOE 0 0 1 1 /1 /2 R 0 QA0:QA1
PIN ASSIGNMENT
GND GND GND GND VDDB VDDA VDDB QA0 QA1 QB0 QB1 QB2 nc
MR/nOE CLK_SEL VDD CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
nc GND QC0 VDDC QC1 GND QC2 VDDC QC3 GND GND QD5 nc
ICS87949I-147
33 32 31 30 29 28
10 11 12
13 27 14 15 16 17 18 19 20 21 22 23 24 25 26
nc GND QD0 VDDD QD1 GND QD2 VDDD QD3 GND QD4 VDDD nc
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View
87949AYI-147
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1
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
Type Input Description Active High Master Reset. Active Low output enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated Pulldown (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS / LVTTL interface levels. Core supply pin. Pullup Pullup Pulldown Pulldown Pulldown Pulldown Pulldown LVCMOS / LVTTL clock inputs. Inver ting differential LVPECL clock input. PCLK select input. When HIGH, selects LVPECL clock input. When LOW, selects single ended clock input. LVCMOS / LVTTL interface levels. Controls frequency division for Bank A outputs. LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. LVCMOS / LVTTL interface levels. Power supply ground. No connect. Bank D outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank D outputs. Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank C outputs. Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Bank A outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pin for Bank A outputs.
ICS87949I-147
TABLE 1. PIN DESCRIPTIONS
Number 1 Name MR/nOE
2 3 4, 5 6 7 8 9 10 11 12 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 14, 26, 27, 39, 40 16, 18, 20, 22, 24, 28 17, 21, 25 31, 33, 35, 37 32, 36 41, 45 42, 44, 46 49, 51 50
CLK_SEL VDD CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND nc QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC VDDB QB2, QB1, QB0 QA1, QA0 VDDA
Input Power Input Input Input Input Input Input Input Input Power Unused Output Power Output Power Power Output Output Power
Pulldown Non-inver ting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI-147
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REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 51 3.47V 2.625V 5 23 16 7 12 Maximum Units pF k k pF pF
ICS87949I-147
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0, QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0:QB2 QC0:QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0:QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2
87949AYI-147
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3
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87949I-147
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40C TO 85C
Symbol VDD VDDx IDD Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Core Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 60 20 Units V V mA mA
Output Power Supply Current; NOTE 2 IDDx NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD. NOTE 2: IDDx denotes the sum of IDDA, IDDB, IDDC, IDDD.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40C TO 85C
Symbol VIH VIL VPP VCMR IIH Parameter Input High Voltage DIV_SELA:DIV_SELD, PCLK_SEL, CLK_SEL, Input MR/nOE Low Voltage CLK0, CLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input MR/nOE High Current CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input MR/nOE Low Current CLK0, CLK1 Output High Voltage Test Conditions Minimum 2 -0.3 -0.3 0.3 GND + 1.5 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V IOH = -20mA -5 -150 2.5 0.4 Typical Maximum VDD + 0.3 0.8 1.3 1 VDD 15 0 5 Units V V V V V A A A A V V
IIL VOH
VOL Output Low Voltage IOL = 20mA NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87949AYI-147
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4
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 60 20 Units V V mA mA
ICS87949I-147
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDx IDD Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Core Power Supply Current
Output Power Supply Current; NOTE 2 IDDx NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD. NOTE 2: IDDx denotes the sum of IDDA, IDDB, IDDC, IDDD.
TABLE 4D. DC CHARACTERISTICS, VDD = VDDX = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL VPP VCMR IIH Parameter Input High Voltage DIV_SELA:DIV_SELD, PCLK_SEL, CLK_SEL, Input MR/nOE Low Voltage CLK0, CLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input MR/nOE High Current CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input MR/nOE Low Current CLK0, CLK1 Output High Voltage Test Conditions Minimum 2 -0.3 -0.3 0.3 GND + 1.5 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V IOH = -20mA -5 -150 1.8 0.4 Typical Maximum VDD + 0.3 0.8 1.3 1 VDD 15 0 5 Units V V V V V A A A A V V
IIL VOH
VOL Output Low Voltage IOL = 20mA NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87949AYI-147
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5
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions PCLK, nPCLK CLK0, CLK1 Measured on the rising edge at VDDx/2 Measured on the rising edge at VDDx/2 Measured on the rising edge at VDDx/2 20% to 80% 20% to 80% 400 400 40 Minimum 2.1 2.1 Typical Maximum 200 4.2 5 65 300 1 950 950 60 5 Units MHz ns ns ps ps ns ps ps % ns
ICS87949I-147
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40C TO 85C
Symbol fMAX tPD Parameter Input Frequency Propagation Delay; NOTE 1 Bank Skew: NOTE 2 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time Output Fall Time Output Duty Cycle Output Enable Time; NOTE 5
tsk(b) tsk(o) tsk(pp)
tR tF odc tPZL, tPZH
tPLZ, tPHZ Output Disable Time; NOTE 5 5 ns NOTE 1: Measured from the VDD/2 or crosspoint of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDX = 2.5V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Input Frequency Propagation Delay; NOTE 1 Bank Skew: NOTE 2 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time Output Fall Time Output Duty Cycle Output Enable Time; NOTE 5 Measured on the rising edge at VDDx/2 Measured on the rising edge at VDDx/2 Measured on the rising edge at VDDx/2 20% to 80% 20% to 80% 400 400 40 2.5 Test Conditions Minimum Typical Maximum 250 5.2 55 250 1.5 950 950 60 5 Units MHz ns ps ps ns ps ps % ns
tsk(b) tsk(o) tsk(pp)
tR tF odc tPZL, tPZH
5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 NOTE 1: Measured from the VDD/2 or crosspoint of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87949AYI-147
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6
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
ICS87949I-147
PARAMETER MEASUREMENT INFORMATION
1.65V0.15V 1.25V5%
VDD, V DDx
SCOPE
Qx
VDD , VDDx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V0.15V
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
nPCLK Qx
DDx
2
V
PCLK
PP
Cross Points
V
CMR
V
Qy
DDx
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
PART 1 Qx
OUTPUT SKEW
80% Clock Outputs 80% VOD 20% tR tF 20%
V
DDx
2
PART 2 Qy
V
DDx
2 tsk(pp)
PART-TO-PART SKEW
V
OUTPUT RISE/FALL TIME
DDx
QAx, QBx, QCx, QDx
2
CLK0, CLK1
VDD 2
t PW
t
PERIOD
nPCLK PCLK
odc =
t PW t PERIOD
x 100%
VDDx 2
QAx,QBx, QCx, QDx
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87949AYI-147
PROPAGATION DELAY
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REV. C JUNE 13, 2005
tPD
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
ICS87949I-147
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 1A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 Zo = 50 Ohm C2 3.3V 3.3V LVPECL Zo = 50 Ohm C1
3.3V 3.3V R3 84 R4 84 PCLK
R4 125
nPCLK
HiPerClockS PCLK/nPCLK
R1 125
R2 125
FIGURE 1C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 1D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 120
nPCLK
HiPerClockS PC L K/n PCL K
R1 120
R2 120
R1 1K
R2 1K
FIGURE 1E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
87949AYI-147
FIGURE 1F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
ICS87949I-147
TABLE 6.
JAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
58.0C/W 42.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949I-147 is: 1545 Pin compatible to the MPC949
87949AYI-147
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9
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
52 LEAD LQFP
ICS87949I-147
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b b1 D D1 E E1 e ccc ddd 0.45 --0.05 1.35 0.22 0.22 BCC MINIMUM NOMINAL 52 --1.40 0.32 0.30 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC --0.10 0.13 1.60 0.15 1.45 0.38 0.33 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87949AYI-147
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10
REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
Package 52 Lead LQFP 52 Lead LQFP 52 Lead "Lead-Free" LQFP 52 Lead "Lead-Free" LQFP Shipping Packaging tray 500 tape & reel tray 500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
ICS87949I-147
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87949AYI-147 ICS87949AYI-147T ICS87949AYI-147LF ICS87949AYI-147LFT Marking 7949AI147 7949AI147 TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87949AYI-147
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REV. C JUNE 13, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Pin Description Table - revised MR/nOE description. In 3.3V DC and AC tables, changed VDD = VDDx from 3.3V 5% to 3.3V 0.3V. In 3.3V & 2.5V DC Characteristics tables - VIL row, spec input controls separately from input clocks. 3.3V Output Load Test Circuit Diagram, changed VDD equation to read 1.65V0.15V from 1.65V5%. Revised and replaced Package Outline diagram to correspond with Package Dimensions table. Pin Description Table - changed VDD description to read Core supply pin from Positive supply pin. Power Supply Characteristics table - changed VDD description to read Core Supply Voltage from Positive Supply Voltage. Listed Bank Skew in Features Section. Updated MR/nOE description. Pin Characteristics Table - change CIN to read 4pF typ. from 4pF max. ROUT added 5 min. and 12 max. AC Characteristics Tables, added Bank Skew entries. Features Section - added Lead-Free bullet. Added LVPECL Clock Input Interface section. Ordering Information Table - added Lead-Free par t number. 11/21/02 08/27/02 Date
ICS87949I-147
Rev
Table 1 4A, 4B, 5A
Page 2 4, 5 4, 6 7 9
B
4B, 4D
B
T1 T4A, T4C
2 4, 5 1 2 3 6 1 8 11
C
T1 T2 T5A, T5B
09/15/03
C T8
6/13/05
87949AYI-147
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